This invention relates to a bipolar logic circuit, and more particularly to improvements in a circuit which serves to discharge charges stored in the base of an output transistor when an output changes from "L" (a low level) to "" (a high level).
FIG. 5 illustrates a single-input buffer circuit having a base charge-discharging circuit which is shown in, for example, '85 MITSUBISHI SEMICONDUCTORS, BIPOLAR DIGITAL IC &lt;LSTTL&gt;. Referring to the figure, numeral 1 designates an NPN-type SBD (Schottky barrier diode) clamped transistor, and numerals 2 and 3 designate resistors set at predetermined resistances. A base charge-discharging circuit is constructed of the transistor 1 and the resistors 2, 3. Numeral 4 designates an input terminal, and numeral 5 an input PNP-transistor the base of which is connected to the input terminal 4. Shown at numerals 6, 7, 8, 12, 13 and 15 are NPN-type SBD clamped transistors. Numeral 16 designates an NPN-transistor, and this transistor and the transistor 15 are Darlington-connected to construct an output Darlington Transistor. The output Darlington transistor and the transistor 13 are connected in series between a high potential source terminal 11 and a low potential source terminal 17. In addition, the emitter of the transistor 12 is connected to the base of the transistor 13 at a node, and the base charge-discharging circuit stated above is connected between the node of the transistors 12 and 13 and the low potential source terminal 17. Besides, the base of the transistor 12 is connected to the high potential source terminal 11 through a resistor 10. Numerals 9, 18, 19, 20 and 21 denote Schottky barrier diodes (SBD's). The anode of the SED 9 is connected to the base of the transistor 12, and has its cathode connected to the collector of the transistor 8. Numeral 14 indicates an output terminal, and numerals 22-28 indicate resistors.
Next, the operation of the prior-art circuit will be described.
In a case where an "H" (high) voltage has been applied to the input terminal 4, the input PNP-transistor 5 turns "OFF", the transistors 6, 7 and 8 turn "ON," the transistor 12 turns "OFF," and the output Darlington transistor 15, 16 turns "ON," so that the output terminal 14 becomes an "H" voltage.
In a case where an "L" (low) voltage has been applied to the input terminal 4, the input PNP-transistor 5 turns "ON," the transistors 6, 7 and 8 turn "OFF," and the transistors 12 and 13 turn "ON," so that the output terminal 14 becomes an "L" voltage. Besides, in a case where the voltage applied to the input terminal 4 has changed from "L" to "H", also the level of the output terminal 14 changes from "L" to "H". Under such a state, the transistor 1 forms a discharge path for charges stored in the base of the transistor 13, to shorten the turn-off time of the transistor 13 and to reduce the transient current thereof.
The prior-art bipolar logic circuit is constructed and operatred as described above, and the transistor 13 turns "OFF" after the transistor 12 has turned "OFF". Accordingly, there have been the problems that the circuit has an undesirably slow high-speed performance and a transient current flows through the circuit.